1. Field of the Disclosure
Embodiments of the present disclosure generally relate to the field of electronic devices and, more particularly, to calibration of single-ended high-speed interfaces.
2. Description of the Related Art
An interface may include one or more single-wire connections, and a single-ended driver may thus drive a signal on the single-wire connection. A single-wire connection may include, for example, a Dynamic Random Access Memory (DRAM) interface.
It has been determined that conventional differential interfaces draw constant power during operation regardless of state (e.g., 0 or 1) and do not have optimal bandwidth or pin, which makes them unsuitable for mobile chip-to-chip communications. Single-ended interfaces suffer from high dynamic (e.g., CV2) or static (e.g., V2/R) loads and thus compromise supply signal integrity leading to lower data rates. Conventional high-speed memory standards use VDD/2 (e.g., 600 mV) signaling that provides a factor of four in power efficiency as compared to full swing (e.g., 1.2V CMOS).
At such low signal swings, power noise, ground noise, VREF noise and accuracy play important roles in signal integrity for single-ended communications. The conventional approach of simply designing components and systems to work together is insufficient because specified tolerances approach operating points. The conventional calibration method depends on common VREF sources shared by different devices, which might not match when used internally by different devices, and resistors that are not calibrated, but controlled in steps that cause quantization errors, have process-voltage-temperature (PVT) variations, and exhibit poor linearity.